𝑻𝒓𝒂𝒑 𝑺𝒚𝒔𝒕𝒆𝒎 𝒊𝒏 𝑨𝑼𝑹𝑰𝑿 𝑻𝑪𝟑𝟕𝟓𝑳𝑲

A trap in the AURIX TC375LK architecture (Tricore TC162P) system occurs due to events such as Non-Maskable Interrupts (NMI), instruction exceptions, memory management exceptions, or illegal accesses. Unlike other interrupt systems, traps are always active and cannot be disabled by software. The TriCore architecture contains eight trap classes and these are further classified as synchronous or asynchronous, hardware or software.( As seen in the Image)

Trap Types:

The TriCore architecture specifies eight overarching classes for traps. Each class possesses its unique trap handler, which can be accessed via a trap vector, spanning 32 bytes per entry, indexed by the hardware-defined trap class number. Specific traps within each class are identified by a Trap Identification Number. By categorizing traps and providing dedicated handlers for each type, the system ensures reliable and secure operations, especially in scenarios demanding real-time responses.

Traps can be categorized based on their nature and source:

𝑺𝒚𝒏𝒄𝒉𝒓𝒐𝒏𝒐𝒖𝒔 𝑻𝒓𝒂𝒑𝒔: These are directly linked with the execution or attempted execution of specific instructions. The exact instruction causing the trap is identifiable, ensuring that the trap is addressed immediately before any further instruction execution.

𝑨𝒔𝒚𝒏𝒄𝒉𝒓𝒐𝒏𝒐𝒖𝒔 𝑻𝒓𝒂𝒑𝒔: These traps function similarly to interrupts. They are tied to external hardware conditions. While some arise from previously executed instructions, others, like the Non-Maskable Interrupt (NMI), are purely external events. Unlike standard interrupts, asynchronous traps utilize the trap vector instead of the interrupt vector, making them non-maskable and immune to changes in the current CPU interrupt priority number.

𝑯𝒂𝒓𝒅𝒘𝒂𝒓𝒆 𝑻𝒓𝒂𝒑𝒔: Generated due to exception conditions detected by hardware. Many times, these exceptions relate to the execution of a particular instruction, like illegal instruction traps or memory protection traps.

𝑺𝒐𝒇𝒕𝒘𝒂𝒓𝒆 𝑻𝒓𝒂𝒑𝒔: Intentionally generated as a result of executing system calls or assertion instructions.

𝑼𝒏𝒓𝒆𝒄𝒐𝒗𝒆𝒓𝒂𝒃𝒍𝒆 𝑻𝒓𝒂𝒑𝒔: These are traps from which software cannot recover. In the TriCore architecture, the fatal context trap (FCU) is such an unrecoverable error.

𝑻𝒓𝒂𝒑 𝑯𝒂𝒏𝒅𝒍𝒊𝒏𝒈:

When handling traps, the procedures differ slightly from those for external or software interrupts. Notably, a trap does not alter the CPU interrupt priority, leaving the ICR.CCPN field unchanged.

𝑻𝒓𝒂𝒑 𝑽𝒆𝒄𝒕𝒐𝒓 𝑭𝒐𝒓𝒎𝒂𝒕:: The trap handler vectors are stored in code memory within the trap vector table. The Base address of this table is specified by the BTV register. If a trap handler is concise, it may fit entirely within the designated space in the vector code segment. Otherwise, the segment will contain initial instructions, succeeded by a jump to the rest of the handler.

𝑨𝒄𝒄𝒆𝒔𝒔𝒊𝒏𝒈 𝒕𝒉𝒆 𝑻𝒓𝒂𝒑 𝑽𝒆𝒄𝒕𝒐𝒓 𝑻𝒂𝒃𝒍𝒆: Upon a trap occurrence, a trap identifier is generated. This identifier comprises two components: The Trap Class Number (TCN) and the Trap Identification Number (TIN). The TCN is used to index into the trap vector table, while the TIN is loaded into the data register D[15].

𝑹𝒆𝒕𝒖𝒓𝒏 𝑨𝒅𝒅𝒓𝒆𝒔𝒔 (𝑹𝑨): For synchronous traps, the return address is the PC of the instruction causing the trap. Asynchronous traps, on the other hand, have their return address set to the next instruction that would have been executed.

𝑻𝒓𝒂𝒑 𝑽𝒆𝒄𝒕𝒐𝒓 𝑻𝒂𝒃𝒍𝒆: The entry-points for all Trap Service Routines are stored in the Trap Vector Table in memory. The BTV register specifies the base address of this table. When a trap event arises, a trap identifier, comprising a Trap Class Number (TCN) and a Trap Identification Number (TIN), is generated by the hardware.

𝑰𝒏𝒊𝒕𝒊𝒂𝒍 𝑺𝒕𝒂𝒕𝒆 𝒖𝒑𝒐𝒏 𝒂 𝑻𝒓𝒂𝒑: When a trap arises, specific actions are taken to preserve the system’s state and ensure smooth execution of the trap handler. These actions include saving the upper context, updating the return address, and loading the TIN into D[15].

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An Article by: Yashwanth Naidu Tikkisetty
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