{"id":4345,"date":"2024-06-17T09:40:44","date_gmt":"2024-06-17T04:10:44","guid":{"rendered":"https:\/\/cthecosmos.com\/?p=4345"},"modified":"2024-06-17T09:40:44","modified_gmt":"2024-06-17T04:10:44","slug":"l1-l2-l3","status":"publish","type":"post","link":"https:\/\/cthecosmos.com\/?p=4345","title":{"rendered":"L1 | L2 | L3"},"content":{"rendered":"\n

The L1, L2, and L3 caches are crucial components in modern computing architectures, playing a pivotal role in bridging the speed gap between the ultra-fast CPU and the relatively slower main memory (RAM). Let’s have a overview on these cache levels

1. \ud835\udc73\ud835\udc90\ud835\udc84\ud835\udc82\ud835\udc95\ud835\udc8a\ud835\udc90\ud835\udc8f & \ud835\udc77\ud835\udc93\ud835\udc90\ud835\udc99\ud835\udc8a\ud835\udc8e\ud835\udc8a\ud835\udc95\ud835\udc9a:

\ud835\udc73\ud835\udfcf: Directly integrated into the processor core, ensuring minimal access latency.
It’s the primary cache used by the CPU to store instructions and data for immediate processing.

\ud835\udc73\ud835\udfd0:\u00a0L2 cache is either located on the CPU chip or situated very close to it on the same die.
\ud835\udc73\ud835\udfd1:\u00a0Located on the CPU die but may serve multiple cores, making it a shared resource.

2. \ud835\udc7a\ud835\udc8a\ud835\udc9b\ud835\udc86 & \ud835\udc7a\ud835\udc91\ud835\udc86\ud835\udc86\ud835\udc85:

\ud835\udc73\ud835\udfcf: ~16KB to 128KB per core. Latency is ~ 0.5 to 1.5 ns. Offers the fastest access time due to its proximity to the CPU core.
\ud835\udc73\ud835\udfd0: ~256KB to 512KB per core, but can vary. Latency is ~ 5 to 14 ns.
\ud835\udc73\ud835\udfd1: Ranges widely from 2MB to 50MB or more, shared across all cores. Latency, ~2 to 50 ns, depending on the architecture and distance from the core.


3. \ud835\udc7a\ud835\udc95\ud835\udc93\ud835\udc96\ud835\udc84\ud835\udc95\ud835\udc96\ud835\udc93\ud835\udc86 & \ud835\udc76\ud835\udc93\ud835\udc88\ud835\udc82\ud835\udc8f\ud835\udc8a\ud835\udc9b\ud835\udc82\ud835\udc95\ud835\udc8a\ud835\udc90\ud835\udc8f:

\ud835\udc73\ud835\udfcf: Often split into two:

I-Cache (Instruction Cache): Dedicated to holding the upcoming instructions for the CPU. Often uses a direct-mapped or 2-way set associative structure.

D-Cache (Data Cache): Contains data for instructions. Typically uses a 2-way or 4-way set associative structure.
Cache line\/block size is typically 32 or 64 bytes.

\ud835\udc73\ud835\udfd0: Can be unified (holding both data and instructions) or split like L1.
Typically uses a more highly associative structure than L1, like 8-way or 16-way set associative.
Similar to L1, typically 32 or 64 bytes for cache line size.

\ud835\udc73\ud835\udfd1: Typically unified. More highly associative than L2, with designs like 16-way or 32-way set associative structures being common. Generally has\u00a064 bytes for cache line size.

4. \ud835\udc79\ud835\udc86\ud835\udc91\ud835\udc8d\ud835\udc82\ud835\udc84\ud835\udc86\ud835\udc8e\ud835\udc86\ud835\udc8f\ud835\udc95 \ud835\udc77\ud835\udc90\ud835\udc8d\ud835\udc8a\ud835\udc84\ud835\udc8a\ud835\udc86\ud835\udc94:

\ud835\udc73\ud835\udfcf: Common algorithms like Least Recently Used (LRU) are employed to decide which entries to evict when new data is brought in.
May use write-through or write-back strategies for handling writes.

\ud835\udc73\ud835\udfd0: Common algorithms like Least Recently Used (LRU) are employed to decide which entries to evict when new data is brought in.
May use write-through or write-back strategies for handling writes.

\ud835\udc73\ud835\udfd1: L3 often incorporates advanced prefetching algorithms to anticipate data needs.

Some architectures use a portion of L3 as a “victim cache” for data evicted from L1 or L2, providing a second chance before data is fetched from the slower main memory. Various write policies are employed, similar to L1 and L2


Cache Line<\/strong>: When data is fetched from main memory, it’s fetched in blocks (not individually). This block is referred to as a cache line.

Cache Coherency<\/strong>: Especially in multicore systems, ensuring that all cores have a consistent view of memory is crucial. Protocols like MESI (Modified, Exclusive, Shared, Invalid) are used to manage this.

Cache can handle write operations in various ways:
– Write Through: Write to both the cache and main memory.
– Write Back: Write to the cache first and then write to main memory when the cache line is replaced.
– Write Allocate: On a cache miss during a write, the cache line is loaded from main memory, then written.
– No Write Allocate: On a cache miss during a write, the data is written to main memory, not the cache.



LinkedIn post: https:\/\/www.linkedin.com\/posts\/t-yashwanth-naidu_embedded-embeddedengineers-embeddedsystems-activity-7120250898420834304-TmhQ\/?utm_source=share&utm_medium=member_desktop<\/a>


<\/p>\n\n\n\n

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
An Article by: <\/strong>Yashwanth Naidu Tikkisetty
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~<\/p>\n","protected":false},"excerpt":{"rendered":"

The L1, L2, and L3 caches in modern computing architectures bridge the speed gap between the CPU and RAM. L1 is integrated into the processor core for minimal latency, L2 is close to the CPU, and L3 serves multiple cores. They store instructions and data for immediate processing, with varying sizes and access times. Cache management includes algorithms for evicting entries and handling writes, while cache coherency ensures consistent memory across cores. The cache can handle write operations in different ways.<\/p>\nRead More L1 | L2 | L3<\/span><\/a>","protected":false},"author":120055267,"featured_media":4348,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_feature_clip_id":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":false,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2},"_wpas_customize_per_network":false,"jetpack_post_was_ever_published":false},"categories":[769112296,36985,30181,952411],"tags":[772321202,772321195,29733,46451548,139166765,772321193,1113209,117529,565454,196,1354040],"class_list":["post-4345","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-c-concepts-hub","category-c-programming","category-embedded-systems","category-short-articles","tag-c-concepts-hub","tag-c-programming","tag-cache","tag-cache-coherence","tag-cache-levels","tag-embedded-systems","tag-l1","tag-l2","tag-l3","tag-programming","tag-short-article","fallback-thumbnail"],"aioseo_notices":[],"jetpack_publicize_connections":[],"jetpack_featured_media_url":"https:\/\/i0.wp.com\/cthecosmos.com\/wp-content\/uploads\/2024\/06\/l1l2l3.png?fit=1792%2C1024&ssl=1","jetpack_likes_enabled":true,"jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/p8CiEf-185","jetpack-related-posts":[],"_links":{"self":[{"href":"https:\/\/cthecosmos.com\/index.php?rest_route=\/wp\/v2\/posts\/4345","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/cthecosmos.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/cthecosmos.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/cthecosmos.com\/index.php?rest_route=\/wp\/v2\/users\/120055267"}],"replies":[{"embeddable":true,"href":"https:\/\/cthecosmos.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=4345"}],"version-history":[{"count":4,"href":"https:\/\/cthecosmos.com\/index.php?rest_route=\/wp\/v2\/posts\/4345\/revisions"}],"predecessor-version":[{"id":4351,"href":"https:\/\/cthecosmos.com\/index.php?rest_route=\/wp\/v2\/posts\/4345\/revisions\/4351"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/cthecosmos.com\/index.php?rest_route=\/wp\/v2\/media\/4348"}],"wp:attachment":[{"href":"https:\/\/cthecosmos.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=4345"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/cthecosmos.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=4345"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/cthecosmos.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=4345"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}