WHAT THE FU*K

The Fast Inverse Square Root line of code, ‘i = 0x5f3759df – (i >> 1);’, revolutionized graphics processing in the 90s by efficiently calculating 1/sqrt(x) through bit manipulation and approximation. It exemplified creative programming, significantly enhancing game performance and remains a celebrated part of programming lore and hacker culture.

What is Context Switching

The article explains context switching and details the roles of the scheduler and kernel during the process. It highlights how efficient context switching is crucial for multitasking in operating systems, allowing multiple processes to share system resources seamlessly. For further insights, the article is available in PDF format.

𝑪𝒂𝒄𝒉𝒆 𝑾𝒓𝒊𝒕𝒆 𝑻𝒉𝒓𝒐𝒖𝒈𝒉 𝒂𝒏𝒅 𝑪𝒂𝒄𝒉𝒆 𝑾𝒓𝒊𝒕𝒆 𝑩𝒂𝒄𝒌

Modern computing relies on the efficient interaction of components, particularly involving cache memory. This article explores the Write-Through and Write-Back strategies, detailing their operations, benefits, and drawbacks. Understanding these mechanisms enhances knowledge of the performance dynamics that underpin today’s digital environments.

Ellipsis and Variadic

In C, when a function is called, the arguments are typically placed onto the stack, a region of memory. The function retrieves these arguments from the stack based on the function’s known parameter list. But when the number of arguments is variable, the function needs a way to access these “extra” arguments from the stack. […]

What is CACHE?

In computing, “cache” is a vital component that enhances processor speed and efficiency by storing frequently used data and program instructions. It leverages the principles of temporal and spatial locality to optimize data access. Caching offers benefits such as speed, reduced latency, and improved efficiency but comes with considerations like size, complexity, and cost.

L1 | L2 | L3

The L1, L2, and L3 caches in modern computing architectures bridge the speed gap between the CPU and RAM. L1 is integrated into the processor core for minimal latency, L2 is close to the CPU, and L3 serves multiple cores. They store instructions and data for immediate processing, with varying sizes and access times. Cache management includes algorithms for evicting entries and handling writes, while cache coherency ensures consistent memory across cores. The cache can handle write operations in different ways.

SRAM | DRAM

In the field of computing and embedded systems, SRAM and DRAM serve as crucial types of RAM with distinct differences. SRAM, using flip-flops, enables static data storage and finds use in CPU cache memory. On the contrary, DRAM employs capacitors and transistors for dynamic data storage and is preferred for main system memory. SRAM outpaces DRAM in speed, but DRAM excels in cost-effectiveness and reliability. For more details, please visit the LinkedIn post provided.

𝑾𝒉𝒚 𝒅𝒐 𝒂𝒓𝒓𝒂𝒚 𝒊𝒏𝒅𝒆𝒙 𝒔𝒕𝒂𝒓𝒕 𝒘𝒊𝒕𝒉 𝟎?

Many programming languages, including C, C++, Java, and Python, use zero-based indexing for arrays. This allows for more efficient memory management and aligns with binary logic. Influential languages like C set this precedent, and it facilitates the implementation of certain algorithms and mathematical formulas. However, languages like Fortran, MATLAB, and Lua use one-based indexing as an alternative.

~ 𝐁𝐢𝐭 𝐁𝐚𝐧𝐠𝐢𝐧𝐠 ~

Bit banging is a technique to interface with external devices using standard input/output operations. It involves manually manipulating I/O pins to generate signals, such as for SPI communication when hardware modules are not available. This software-based approach provides direct control over the interface, avoiding the need for specialized hardware. [Original content shortened for length]

𝑫𝒐 𝒚𝒐𝒖 𝒘𝒂𝒏𝒕 𝒕𝒐 𝒈𝒆𝒕 𝒔𝒕𝒂𝒓𝒕𝒆𝒅 𝒘𝒊𝒕𝒉 𝑪 𝒂𝒏𝒅 𝑨𝒔𝒔𝒆𝒎𝒃𝒍𝒚? 𝑯𝑪𝑺𝟏𝟐

The HCS12 microcontroller is designed to emulate the M68HC11 CPU, while expanding its capabilities. It excels in data handling, ROM space efficiency, and instantaneous instruction access. With diverse indexed addressing capabilities and a robust programming model, it efficiently handles various data types and offers an expansive 64-Kbyte standard address space.